MLAB hardware characteristics cause this behavior. The output of an MLAB always updates when a write operation occurs, and the write address is equal to the read address. When writing to the last available location in an MLAB-based SCFIFO megafunction, the full flag is asserted, and the new data is stored and propagated to the output. The SCFIFO output displays the correct data in the cycle after a read request. This behavior occurs during board testing or simulating with the SCFIFO design netlist. This behavior does not happen when simulating with SCFIFO functional model.
This behavior does not occur for SCFIFO mega functions implemented in other memory block types (M512, M4K, M9K, M144K, M20K, and M-RAM). For a SCFIFO mega function implemented in one of these memory block types, when writing to the last available location in the SCFIFO megafunction, the full flag is asserted, and the new data is stored, but the output will not change. The output updates only when the read request is asserted.
SCFIFO mega functions generated with the Quartus® II software versions 7.0 and later with the following settings in the MegaWizard™ Plug-In are affected:
- Normal synchronous FIFO mode is selected for the read access option
- MLAB is selected for the memory block type
- No (smallest area) is selected for the output registers option
To work around this problem, make one of the following changes to your SCFIFO mega function:
- Change the output register option from No (smallest area) to Yes (best speed). Note that the output latency of the SCFIFO mega function is the same in both modes
- Select a different memory block type
The SCFIFO MegaWizard Plug-In will disable the MLAB memory block type option when selecting the Normal synchronous FIFO mode and No (smallest area) options.