Why does the Qsys interconnect has a buswidth mismatch on the burstcount signal?

Due to a problem in the Quartus® II software version 13.1, Qsys may incorrectly generate the bitwidth of burstcount signal when the Avalon-MM component uses the beginbursttransfer_n signal. VHDL design will generate an error for this mismatch.

To work around this problem, change the polarity of the beginbursttransfer_n signal to beginbursttransfer or remove the beginbursttransfer_n signal from Avalon-MM component.

Altera recommends that you do not use this signal for new designs.

This problem is scheduled to be fixed in a future release of the Quartus II software.