Due to a probem in the HPS SDRAM Controller calibration algorithm generated by the Altera SoC Embedded Design Suite for Cyclone® V SoC and Arria® V SoC devices, the DQS enable centre report may be greater than both start and end reports.
The calibration algorithm finds the maximum and minimum parameters for a number of delays and picks the centre value. For DQS enable, both the start and end reports have been normalized to VFIFO_SIZE, but the center report is not normalized, so may appear to be outside of the range start:end.
VFIFO_SIZE is set to 16 for Cyclone V and Arria V devices.
Note: To enable this report the macro RUNTIME_CAL_REPORT must be set, which reports the results of the calibration process to the stdout (usually a UART).
The center VFIFO report should be divided by 16 which is VFIFO_SIZE and the remainder is the VFIFO delay.
For example:
SEQ.C: DQS Enable ; Group 0 ; Rank 0 ; Start VFIFO 6 ; Phase 1 ; Delay 4
SEQ.C: DQS Enable ; Group 0 ; Rank 0 ; End VFIFO 7 ; Phase 0 ; Delay 18
SEQ.C: DQS Enable ; Group 0 ; Rank 0 ; Center VFIFO 22 ; Phase 5 ; Delay 3
The true center VFIFO value is 22 % 16 = 6 which is between 6 and 7 as expected.
The generated preloader code may be modified to make this change as follows:
1. Open <preloader>\uboot-socfpga\board\altera\socfpga\sdram\sequencer.c
2. Search for the following line:RPRINT("DQS Enable ; Group %lu ; Rank %lu ; Center VFIFO %2li ; Phase %li ; Delay %2li", grp, sr, v, p-1, d);
3. Replacing with this line:RPRINT("DQS Enable ; Group %lu ; Rank %lu ; Center VFIFO %2li ; Phase %li ; Delay %2li", grp, sr, (v % VFIFO_SIZE), p-1, d);
4. Regenerate your Preloader by running:
make clean; make.
This problem is sechulded to be resolved in a future release of the Altera SoC Embedded Design Suite .
