You will receive the below critical warning for the Serial Digital Interface (SDI) II IP instance because of the improper connection of the Transmitter parallel clock input (tx_pclk).
Critical Warning (21196): Coreclk source from HSSI 8G TX PCS atom <SDI TX IP instance>|altera_xcvr_native_av:u_phy|av_xcvr_native:gen_native_inst.av_xcvr_native_insts[0].gen_bonded_group_native.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_8g_tx_pcs_rbc:inst_av_hssi_8g_tx_pcs|wys does not have the same 0 ppm source with respect to PCS internal clock because of coreclk input of the Transmitter channel is not connected.
To avoid this critical warning, the Parallel clock input (tx_pclk) of SDI II IP has to driven by the PLL clock output signal for the hard transceiver (tx_clkout) as stated in the SDI II IP User Guide (Link).