You may get the error when instantiating any first-in first-out (FIFO) library of parameterized modules (LPM) function directly. If the instantiated FIFO buffer uses the cell and logs two arithmetic functions, the parameters cannot be passed through the defparam argument. The example below does not work even though it is coded correctly.
. . .
module fifo256x8 (data, rreq, wreq, clock, clockx2, aclr, threshlevel,
threshold, empty, full, usedw, q);
input [7:0] data;
input [7:0] threshlevel;
input rreq, wreq, clock, clockx2, aclr;
output [7:0] q;
output [7:0] usedw;
output threshold, empty, full;
sfifo inst_1 (.data (data),
.rreq (rreq), .wreq (wreq), .clock (clock), .clockx2 (clockx2),
.aclr (aclr), .q (q), .usedw (usedw), .threshold (threshold),
.empty (empty), .threshlevel (threshlevel), .full (full));
defparam inst_1.lpm_width = 8;
defparam inst_1.lpm_numwords = 256;
endmodule
. . .
The workaround is to instantiate the FIFO function in a dummy Graphic Design File (.gdf) file with all of its parameter set and give it a specific name (e.g., my_fifo.gdf). Create a default Include File (.inc) for the GDF. Instantiate the GDF in the top level Verilog HDL code without any parameter specified. The example below will work (corresponding to the example above).
. . .
module fifo256x8 (data, rreq, wreq, clock, clockx2, aclr, threshlevel,
threshold, empty, full, usedw, q);
input [7:0] data;
input [7:0] threshlevel;
input rreq, wreq, clock, clockx2, aclr;
output [7:0] q;
output [7:0] usedw;
output threshold, empty, full;
my_fifo inst_1 (.data (data),
.rreq (rreq), .wreq (wreq), .clock (clock), .clockx2 (clockx2),
.aclr (aclr), .q (q), .usedw (usedw), .threshold (threshold),
.empty (empty), .threshlevel (threshlevel), .full (full));
endmodule
. . .
my_fifo.gdf contains an instantiation of SFIFO with lpm_width = 8 and lpm_numwords = 256. The port mapping above refers to my_fifo.gdf, and not to the SFIFO megafunction.