Why is the Cyclone V SoC Device SDRAM interface Vref pin voltage incorrect ?

In the the Quartus®  II 13.0SP1 release, the Cyclone V SoC Hard Processor System Component SDRAM Interface Vref port is incorrectly configured as an output. If you are generating the Vref with a potential divider, the Vref voltage will be lower than the SDRAM interface requirement, causing the interface to fail calibration.

If the Vref is generated from a DDR termination regulator, this issue may not be seen.

Install the Quartus  II 13.0SP1 release DP5 patch. See the solution below for details :

How do I address known software issues for Stratix V, Arria V and Cyclone V devices in the Quartus II software version 13.0 SP1?

The same fix is also available as a separate patch (1.34) for the Quartus II 13.0SP1 release. It is recommended that users install the DP5 patch, but should a separate patch for only the HPS Vref issue be required, please contact Altera.

This issue will be fixed in a future version of Quartus® II software.