Article ID: 000079943 Content Type: Troubleshooting Last Reviewed: 06/19/2013

Why does the mdio_addr1 signal at offset 0x10 have a value of '0' for the Triple Speed Ethernet IP core?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description Triple Speed Ethernet MegaCore® Function User Guide states that HW reset value for mdio_addr1 is '1'. This is applicable only if the MDIO option is turned on. If the MDIO option is turned off in your Triple Speed Ethernet IP instantiation, the HW reset value for mdio_addr1 is '0'.

Related Products

This article applies to 28 products

Cyclone® V GT FPGA
Cyclone® III FPGAs
Stratix® V GX FPGA
Cyclone® IV GX FPGA
Cyclone® V GX FPGA
Cyclone® II FPGA
Stratix® V GS FPGA
Arria® V GZ FPGA
Stratix® II GX FPGA
Stratix® II FPGAs
Arria® V GX FPGA
Stratix® V GT FPGA
Arria® V GT FPGA
Stratix® III FPGAs
Stratix® IV GX FPGA
Arria® II GX FPGA
Arria® II GZ FPGA
Stratix® IV GT FPGA
Cyclone® V E FPGA
Stratix® V E FPGA
Arria® GX FPGA
Cyclone® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Cyclone® V SE SoC FPGA
Cyclone® IV E FPGA
Arria® V ST SoC FPGA
Cyclone® III LS FPGA
Stratix® IV E FPGA

1

Need more help?

Contact support

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.