Article ID: 000079941 Content Type: Troubleshooting Last Reviewed: 08/16/2012

Stratix V Pin-Out Table: Known Issues

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Issue 63753:  Pin out tables for all Stratix V devices dated July 2012 and earlier

The pin out files do not show that DCLK can be used as a user I/O after configuration when the configuration mode is an Active mode.  DCLK can be used as a regular I/O pin after configuration when the configuration mode is an Active mode

Related Products

This article applies to 4 products

Stratix® V GS FPGA
Stratix® V E FPGA
Stratix® V GX FPGA
Stratix® V GT FPGA

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