Article ID: 000079939 Content Type: Error Messages Last Reviewed: 03/25/2013

Internal Error: Sub-system: ASMPLL, File: /quartus/comp/asmpll/asmpll_28nm.cpp, Line: 231

Environment

    Quartus® II Subscription Edition
    PLL
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a problem in the Quartus® II software version 12.0, you may see this error if your HDL code implements a PLL in normal or source-synchronous mode and drives an external clock output. This problem affects designs targeting Stratix® V, Arria® V, and Cyclone® V devices.

Resolution

To work around this problem, do not use normal or source-synchronous mode and an external clock output at the same time.

The issue is fixed beginning with the Quartus II software version 12.0 SP1.

Related Products

This article applies to 14 products

Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA
Stratix® V GX FPGA
Stratix® V GT FPGA
Cyclone® V GX FPGA
Stratix® V GS FPGA
Arria® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Arria® V ST SoC FPGA
Arria® V GX FPGA
Arria® V GT FPGA
Cyclone® V E FPGA
Stratix® V E FPGA
Cyclone® V SE SoC FPGA

1

Need more help?

Contact support

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.