The PCI Express MegaCore function does not generate the Gen2 compliance pattern for the hard IP implementation in Stratix IV GX devices because the hard IP reset circuitry is holding the transceiver in reset.
This issue affects the hard IP implementation of the PCI Express MegaCore function targeting Stratix IV GX devices that use reset scheme for <variant>.v or .vhd MegaCore function as described the “Reset and Clocks” chapter of the PCI Express Compiler User Guide. (It does not affect the <variant>_plus.v or .vhd MegaCore functions).
The workaround is to modify the definition of the
in <variant>.v or .vhd file
when running the compliance test. shows the required modification
for compliance testing and the definition for normal operation.
In addition, the reserved
test_in bit (
must be defined as an input to the reset circuit to indicate that
the DUT is performing the compliance test. When
set to 1, the portion of the reset circuit which introduces the
compliance bug is bypassed. When this bit is set to 0, the PCI Express
MegaCore function works in normal operating mode.
This issue is fixed in version 10.1 of the PCI Express MegaCore function.