Article ID: 000079915 Content Type: Troubleshooting Last Reviewed: 10/10/2011

PCI Express Compliance Test Does Not Generate Gen2 Compliance Pattern


  • Quartus® II Subscription Edition

    Critical Issue


    The PCI Express MegaCore function does not generate the Gen2 compliance pattern for the hard IP implementation in Stratix IV GX devices because the hard IP reset circuitry is holding the transceiver in reset.

    This issue affects the hard IP implementation of the PCI Express MegaCore function targeting Stratix IV GX devices that use reset scheme for <variant>.v or .vhd MegaCore function as described the “Reset and Clocks” chapter of the PCI Express Compiler User Guide. (It does not affect the <variant>_plus.v or .vhd MegaCore functions).


    The workaround is to modify the definition of the rx_digitalreset_serdes signal in <variant>.v or .vhd file when running the compliance test. shows the required modification for compliance testing and the definition for normal operation.

    Definition of rx_digitalreset_serdes for Compliance Testing and Normal Operation
    // Use this assignment for compliance testing assign rx_digitalreset_serdes = rc_rx_digitalreset; // Use this assignment for operation in non-compliance mode assign rx_digitalreset_serdes = rc_rx_digitalreset | rst_rxpcs;

    In addition, the reserved test_in bit (test_in[32]) must be defined as an input to the reset circuit to indicate that the DUT is performing the compliance test. When test_in[32] is set to 1, the portion of the reset circuit which introduces the compliance bug is bypassed. When this bit is set to 0, the PCI Express MegaCore function works in normal operating mode.

    This issue is fixed in version 10.1 of the PCI Express MegaCore function.

    Related Products

    This article applies to 1 products

    Stratix® IV FPGAs