Article ID: 000079909 Content Type: Troubleshooting Last Reviewed: 03/02/2015

Why is the Arria V GZ Hard IP for PCI Express "Enable HIP Status Bus" always enabled?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The PCI Express® tcl file "altera_pcie_avgz_hip_avmm_hw.tcl" found in the Quartus® II  install directory: \altera\<your_version>\ip\altera\altera_pcie\altera_pcie_avgz_hip_avmm\ is missing the enable_hip_status such that the features are always enabled.

    Resolution The following lines need to be added after the set enable_hip_status_ext section to ensure the Hard IP Status Bus can be enabled and disabled:

     

    set enable_hip_status [ get_parameter_value  CG_ENABLE_HIP_STATUS ]

      if {   == 1 } {

          add_pcie_hip_port_status

          }

     

    This problem is scheduled to be fixed in a future Quartus II software.

    Related Products

    This article applies to 1 products

    Arria® V GZ FPGA

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