Is the PLL output clock maybe imprecise in PLL behavior model for Cyclone IV device?

Yes, PLL output clock might be imprecise under some conditions in PLL behavior model for Cyclone IV device. That's because PLL behavior model only compute output frequency based on the clock multiplication factor and division factor which might miss out some of the fractional values.

For example:

The input clock is 125MHz, multiplication factor is 125 and division factor is 1536, the PLL output clock period is 98286ps by simulation. However the PLL output clock should be 10.172526MHz/98304ps.

As a workaround, user can turn on Advanced PLL feature in the UI, so that PLL behavior model can calculate more precise by using the advance parameter.

The issue is scheduled to be fixed in Quartus ® II software version 12.1.