Article ID: 000079902 Content Type: Troubleshooting Last Reviewed: 08/29/2012

Is the PLL output clock maybe imprecise in PLL behavior model for Cyclone IV device?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Yes, PLL output clock might be imprecise under some conditions in PLL behavior model for Cyclone IV device. That's because PLL behavior model only compute output frequency based on the clock multiplication factor and division factor which might miss out some of the fractional values.

     

    For example:

    The input clock is 125MHz, multiplication factor is 125 and division factor is 1536, the PLL output clock period is 98286ps by simulation. However the PLL output clock should be 10.172526MHz/98304ps.

    Resolution

    As a workaround, user can turn on Advanced PLL feature in the UI, so that PLL behavior model can calculate more precise by using the advance parameter.

    The issue is scheduled to be fixed in Quartus ® II software version 12.1.

     

    Related Products

    This article applies to 2 products

    Cyclone® IV FPGAs
    Cyclone® IV GX FPGA

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