Article ID: 000079896 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Is the Stratix® II PLL lock signal synchronous to the input or output clock or is it an asynchronous signal?

Environment

  • PLL
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The lock signal is an asynchronous output of the PLL.

     

    The PLL lock signal is derived from the reference clock and feedback clock feeding the Phase Frequency Detector (PFD).

     

    Reference clock = Input Clock/N

    Feedback clock = VCO/M

     

    The PLL generates a locked output when the phases and frequencies of the reference clock and feedback(FB) clock are the same or within the lock circuit tolerance.  When the difference between the two inputs at the PFD goes beyond the lock circuit tolerance, the PLL loses lock. The lock signal is a function of the PLL input reference clock and the feedback clock, but not exactly synchronous to those clocks since they must be outside of the lock circuit tolerance before the lock signal is de-asserted.

    Related Products

    This article applies to 2 products

    Stratix® FPGAs
    Stratix® II FPGAs

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