Article ID: 000079878 Content Type: Troubleshooting Last Reviewed: 08/28/2012

Why do I see bit errors on Rx channel 0 of transceiver block GXBL1 when I de-assert the gxb_powerdown signal of transceiver block GXBL0 when using Cyclone IV GX EP4CGX150 and EP4CGX75 devices?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You may see bit errors on Rx channel 0 of transceiver block GXBL1 when you de-assert the gxb_powerdown signal of transceiver block GXBL0 when using Cyclone® IV GX EP4CGX150 and EP4CGX75 devices due to coupling inside the device.

Designs that may be affected are:

  • Cyclone IV GX EP4CGX150 and EP4CGX75 devices that use transceiver banks GXBL0 and GXBL1 AND
  • Rx channel 0 in transceiver bank GXBL1 is used AND
  • Tx Channel 3 in transceiver bank GXBL0 is used AND
  • The gxb_powerdown signals of transceiver banks GXBL0 and GXBL1 are controlled independently.

Affected designs may need to be resynchronized.

Resolution To work around this problem, do not use the gxb_powerdown signal for transceiver bank GXBL0. Instead you can assert the pll_areset, tx_digitalreset, rx_analogreset, and rx_digitalreset signals.

Related Products

This article applies to 3 products

Cyclone® FPGAs
Cyclone® IV FPGAs
Cyclone® IV GX FPGA

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.