Description
This error may occur in the ModelSim® simulator when you use an incorrect coding style for modules. In Verilog-1995, module declarations must not contain the size of the port being declared. They must contain only the name. The size of the port must be declared after the module declaration, where the port type is specified.
For example, the following module declaration is illegal:
module abc (
port_a [15:0],
...
);
The correct way to declare this module is the following:
module abc (
port_a,
...
);
input port_a [15:0];
...;
Changing all modules from the first coding style to the second will allow the design to compile and load in the ModelSim simulator.