Article ID: 000079876 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why do I see hardware functional failures on DDR3 SDRAM interface designs on Stratix IV ES devices using the Quartus II software version 9.0 SP1?

Environment

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Description

There are known issues with the Stratix® IV Engineering Sample (ES) device preliminary timing models in the Quartus® II software versions 9.0 SP1 and earlier, which can cause hardware functional failures on your DDR3 SDRAM interface design.

The issue affects models including the D1, D4, D5, D6, T4 (DDIO_MUX), and write leveling delay chains. The timing models for these delay chains have been updated beginning with the Quartus II software version 9.0 SP2.

To fix the problem, download and install Service Pack 2 for the Quartus II software version 9.0, then recompile your DDR3 SDRAM interface instances to ensure accurate timing analysis and functionality.

There is an additional issue related to delay chains timing in the Quartus II software version 9.0 SP2 Assembler, and a patch is available to fix that issue. Refer to the Related Solution below for more information.

Related Products

This article applies to 3 products

Stratix® IV E FPGA
Stratix® IV GX FPGA
Stratix® IV GT FPGA

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