Description
The Mentor Graphics® ModelSim 5.7 and 5.7a releases have a problem with Verilog HDL non-blocking assignments that have variable delays that are zero in value (e.g.
cout_tmp <= #(time_delay) tmp_cout; where time_delay = 0). The bug results in incorrect simulation results for the Stratix® altpll functional simulation model in the altera_mf.v file.
The problem has been fixed in Mentor Graphics ModelSim version 5.7b release.
