CPRI v6.0 IP Core VHDL Variations That Target an Arria V GZ or Stratix V Device Cannot Simulate With the Synopsys VCS-MX Simulator

VHDL variations of the CPRI v6.0 IP core that target an Arria V GZ or Stratix V device cannot simulate with the Synopsys VCS-MX simulator.

To avoid this issue, you can simulate the IP core with the Mentor Graphics ModelSim simulator.

Alternatively, you can work around this issue with some manual modifications to the generated RTL code. After you generate your design, you must manually modify the pll_sim.vhd file that the external TX PLL IP core generates, before simulating your design.

You must modify the type in the declarations and logic for the pll_fb_sw, fboutclk, and hclk signals to std_logic_vector, by making the following changes in the file:

In the component declaration, replace this text

with this text:

In the port map, replace this text

with this text:

This issue is fixed in version 14.1 of the CPRI v6.0 IP core.