Article ID: 000079787 Content Type: Troubleshooting Last Reviewed: 05/13/2016

For LPDDR3 Interfaces on Arria 10 Devices, all 4 Pairs of CK Pins Must be Reserved

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    For each LPDDR3 interface in your design, you must reserve all four pairs of CK pins, regardless of which pins are required by the design. The CK pins cannot be used for any purpose other than CK. Lanes containing unused CK pins cannot be used as DQ lanes. Unreserved pins can still be used as general purpose I/O pins.

    Resolution

    There is no workaround for this limitation.

    This problem is fixed in version 16.0.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs