Downstream memory reads (MRds) fail for all variants of the Arria V Hard IP for PCI Express IP core. No MRd TLP is generated on the Avalon Streaming (Avalon-ST) RX bus.
The workaround is to drive the
with application logic or from an input pin instead of connecting
it to ground. Connecting
rx_st_mask to application logic
or an input pin prevents the Quartus II software from removing rx_st_mask during
optimization. For more information about the rx_st_mask signal,
refer to the
Arria V Hard IP for PCI Express User Guide.
This issue is fixed in version 12.0 of the Quartus II software.