Article ID: 000079775 Content Type: Troubleshooting Last Reviewed: 03/13/2013

Which clock are the tx_ready and rx_ready status signals synchronous to in the Altera Transceiver PHY IP core?

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Description The tx_ready and rx_ready status signals are synchronous to the phy_mgmt_clk as they are generated from the embedded reset controller which runs off the phy_mgmt_clk.

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Stratix® IV GT FPGA

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