Some RapidIO II IP Core Register Bits Do Not Behave as Specified

The following register bits in the RapidIO II IP core do not behave as specified:

Port Degraded Interrupt Enable (PORT_DEGR_IRQ_EN) field of the Port 0 Control CSR: This implementation-defined bit has no effect. Instead, the Port Failed Interrupt Enable (PORT_FAIL_IRQ_EN) field of the Port 0 Control CSR controls whether or not the RapidIO II IP core asserts the std_reg_mnt_irq interrupt signal when it (the IP core) raises the port_degraded signal.

Transmitter Mode field of the LP-Serial Lane n Status 0 register: This bit is controlled by writing to the Transmitter Type field (bit [19]) of the LP-Serial Lane n Status 0 register, rather than writing to the Transmitter Mode field (bit [18]). When the application writes to the Transmitter Type field, the value of the Transmitter Type field does not change.

This issue has no workaround.

This issue is fixed in version 13.0 of the RapidIO II MegaCore function.