Article ID: 000079723 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why does DDR SDRAM, DDR2 SDRAM and DDR3 SDRAM Altmemphy and UniPHY based controllers violate the maximum refresh interval specified in the memory preset editor in the controller GUI?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The controller does not guarantee that refresh will happen within the specified time in the preset editor. Depending on what the controller is doing and bank state this could take a while. When refresh interrupt happens during sequential burst transactions it could be 135ns later than the optimal time.

Workaround is to decrease tREFI in preset editor to a working value of 7.6us. This 200ns reduction is recommended by Altera to be on the safe side.

Related Products

This article applies to 9 products

Cyclone® IV GX FPGA
Cyclone® III LS FPGA
Cyclone® III FPGAs
Stratix® V GX FPGA
Stratix® IV GT FPGA
Stratix® IV E FPGA
Stratix® IV GX FPGA
Stratix® III FPGAs
Arria® II GX FPGA

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.