Hard IP for PCI Express IP Core RX Interface Not in High Impedance when PERST Is Asserted

When the nPERSTL* pin is holding the Hard IP for PCI Express IP cores in reset, the RX interface is not in high impedance. Instead, the RX interface shows about 1K ohm impedance. If the link partner performs receiver detect at this time, it might not be able to detect some receiver lanes. If the link partner does not detect all lanes, when the Hard IP exits reset and begins link training, the link may downtrain. And, the link may exclude some lanes that are actually available. This problem may occur in the following devices: Arria V, Arria V GZ, Arria 10, Cyclone V, Stratix V and Stratix 10 using the L-tile.

Use synchronous resets. The Hard IP for PCI Express IP Core should exit reset at the same or earlier than its link partner.