The Quartus® II compiler fails for Stratix II GX designs with transceivers configured in bonded x4 (PCI Express (PIPE) x4, XAUI and Basic x4) and bonded x8 (PCI Express (PIPE) x8) configurations depending on channel placement.

Quartus® II software requires specific channel placements for the following bonded channel configurations to compile the design succesfully.

1) x4 Bonded Channel Configurations:

In PCI Express (PIPE) x4 and XAUI modes, both the transmitter and receiver channels are bonded. In Basic x4 mode, only the transmitter channels are bonded.

a) For a PCI Express (PIPE) x4 or XAUI implementation, you must connect the ALT2GXB logical channels to the physical channels as follows:

• Logical Channel 0 (tx_dataout[0]/rx_datain[0]) -> Physical Channel 0 in the Transceiver Block
• Logical Channel 1 (tx_dataout[1]/rx_datain[1])  -> Physical Channel 1 in the Transceiver Block
• Logical Channel 2  (tx_dataout[2]/rx_datain[2]) -> Physical Channel 2 in the Transceiver Block
• Logical Channel 3  (tx_dataout[3]/rx_datain[3]) -> Physical Channel 3 in the Transceiver Block

 b) For a Basic x4 implementation, you must connect the ALT2GXB logical channels to the physical channels as follows:

• Logical Channel 0 (tx_dataout[0]) -> Physical Channel 0 in the Transceiver Block
• Logical Channel 1 (tx_dataout[1]) -> Physical Channel 1 in the Transceiver Block
• Logical Channel 2 (tx_dataout[2]) -> Physical Channel 2 in the Transceiver Block
• Logical Channel 3 (tx_dataout[3]) -> Physical Channel 3 in the Transceiver Block

 The Quartus® II software generates compilation errors when the logical channels are not connected to the physical channels as recommended above.

For a x4 bonded configuration, Altera recommends connecting the physical channels 0, 1, 2, and 3 in the Transceiver block to the respective connector’s Lanes 0, 1, 2, and 3, respectively. 

Figure 1.Shows the legal physical channel to x4 lane mapping in Stratix II GX devices with four transceiver blocks.

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 2) x8 Bonded Channel Configurations:

For a PCI Express (PIPE) x8 implementation, you must connect the ALT2GXB logical channels to the physical channels as follows:

• Logical Channel 0 (tx_dataout[0]/rx_datain[0]) -> Physical Channel 0 in the Master Transceiver Block
• Logical Channel 1 (tx_dataout[1]/rx_datain[1]) -> Physical Channel 1 in the Master Transceiver Block
• Logical Channel 2 (tx_dataout[2]/rx_datain[2]) -> Physical Channel 2 in the Master Transceiver Block
• Logical Channel 3 (tx_dataout[3]/rx_datain[3])  -> Physical Channel 3 in the Master Transceiver Block
• Logical Channel 4 (tx_dataout[4]/rx_datain[4]) -> Physical Channel 0 in the Slave Transceiver Block
• Logical Channel 5 (tx_dataout[5]/rx_datain[5]) -> Physical Channel 1 in the Slave Transceiver Block
• Logical Channel 6 (tx_dataout[6]/rx_datain[6]) -> Physical Channel 2 in the Slave Transceiver Block
• Logical Channel 7 (tx_dataout[7]/rx_datain[7]) -> Physical Channel 3 in the Slave Transceiver Block

The Quartus® II software generates compilation errors when the logical channels are not connected to the physical channels as recommended above.

For a PCI Express x8 link, Altera recommends connecting the physical channels 0, 1, 2, 3, 4, 5, 6, and 7 in the transceiver block to the PCI Express edge connector Lanes 0, 1, 2, 3, 4, 5, 6, and 7, respectively. 

Figure 2.Shows the legal physical channel to PCI Express x8 lane mapping in Stratix II GX devices with four transceiver blocks.

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For legal physical channel to PCI Express x8 lane mapping in all other Stratix II GX devices, refer to the “Transceiver Clock Distribution” section in the “Stratix II GX Transceiver Architecture Overview” chapter in volume 2 of the Stratix II GX Device Handbook.