Article ID: 000079713 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why do some IP MegaCores with a valid license fail to compile with Stratix V devices?



Due to a problem with the Quartus® II software versions 10.1 and later, designs containing IP MegaCore® functions from the list below may cause compilation to stop with a license error even if you have a valid IP MegaCore license. This is due to a bug in the encryption of these cores for Stratix® V devices. The list of affected cores is:

  • POS-PHY Level 4
  • Reed Solomon
  • Viterbi
  • CIC
  • FIR Compiler
  • NCO
  • FFT
  • Alpha Blending Mixer
  • CSC
  • Chroma Resampler
  • Clipper
  • Color Plane Sequencer
  • Deinterlacer
  • FIR Filter 2D
  • Frame Buffer
  • Gamma Corrector
  • Interlacer
  • Median filter 2D
  • Scaler
  • Test Pattern Generator
  • Triple Speed Ethernet

A typical error message (using the Triple Speed Ethernet core as an example) looks like:

Error: Core "Triple Speed Ethernet" (6AF7_00BD) is not enabled for current device family

Affected Configurations

All variations of the above cores targeting the Stratix V device family using version 10.1 or later.


A patch is available to fix this problem for the Quartus II software version 10.1 SP1. If you are using the Quartus II software version 10.1, you must upgrade to 10.1 SP1 before using this patch.  Download and install patch 1.19 from the appropriate link below:

This problem is scheduled to be fixed in a future version of the Quartus II software.

Related Products

This article applies to 1 products

Stratix® V GX FPGA



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