Article ID: 000079663 Content Type: Troubleshooting Last Reviewed: 11/11/2011

C106 Warnings for Interlaken MegaCore Function 10- and 20-Lane Variations With Transceivers

Environment

    Quartus® II Subscription Edition
    Interlaken
BUILT IN - ARTICLE INTRO SECOND COMPONENT

Critical Issue

Description

When you compile an Interlaken MegaCore function 10- or 20-lane variation with transceivers, the following warning message appears:

Warning: (Medium) Rule C106:Clock signal source should not drive registers triggered by different clock edges.

Resolution

This issue has no workaround. However, this issue has no design impact. You can ignore this warning message.

This issue will be fixed in a future version of the Interlaken MegaCore function.

Related Products

This article applies to 1 products

Intel® Programmable Devices

1

Need more help?

Contact support

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.