Article ID: 000079657 Content Type: Error Messages Last Reviewed: 09/11/2012

Internal Error: Sub-system: VPR20KMAIN, File: /quartus/fitter/vpr20k/vpr_common/cbe_block_creator.c, Line: 2945



This error may occur in the Quartus® II software version 10.0 and earlier if your design contains an ALTIOBUF megafunction with the Enable input buffer dynamic delay chain option selected, and when the megafunction directly connects to user-coded DDR input logic. This error affects all device families supporting the dynamic delay chain option including Stratix® III, Stratix IV and Stratix V devices.

The implementation of the dynamic delay chain requires that the ALTIOBUF megafunction connect directly to the dedicated DDR input registers in the IO cell. However, the Quartus II software does not support inference of the dedicated DDR input registers.

To work around this problem, replace your user-coded DDR input logic with an ALTDDIO_IN megafunction equivalent which can be generated using the MegaWizard™ Plug-In Manager

This problem is scheduled to be fixed in a future version of the Quartus II software.

Related Products

This article applies to 6 products

Stratix® IV GT FPGA
Stratix® IV E FPGA
Stratix® IV GX FPGA
Stratix® III FPGAs
Stratix® V GX FPGA
Stratix® V GS FPGA



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