Article ID: 000079642 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why is there no recovery and removal timing report for my memory interface design constrained with DTW (the DDR Timing Wizard)?



There may be no recovery and removal report for such a design if you have not cut the postamble path in the design.

To see if this might be the issue, first check if the postamble path is cut using one of the following methods:

  • For the Classic Timing Analyzer, open the Assignment Editor in the Quartus® II software and ensure that nodes ending with |dqs_io~regout in the From column have a Cut Timing Path assignment set to On. There should be one assignment for each DQS group.
  • For the TimeQuest Timing Analyzer, use the Report SDC task and check the False Path report.

Note that the node names may be different depending on the name you use for the controller. An example of the full name of the node is as follows: my_core:my_core_ddr_sdram| my_core_auk_ddr_sdram:my_core_auk_ddr_sdram_inst|my_core_auk_ddr_datapath:ddr_io| my_core_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|dqs_io~regout

my_core is the name of the variation of the controller, and "g_datapath:0" indicates the DQS group numbering.

Related Products

This article applies to 1 products

Stratix® II FPGAs



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