Description
This problem can seem like a hold time violation in the silicon when compiled by using the Quartus II 3.0 SP2 software. This error occurs when using byte alignment (L1 tap) for the LVDS block.
Patch 2.35 is available at request for the Quartus II 3.0 SP2 version only. This will mean that any design that uses byte-alignment (L1 tap) will have incorrect SOF. The fix will be to also check for enableout port types while checking for the connectivity.
