Article ID: 000079613 Content Type: Product Information & Documentation Last Reviewed: 09/12/2012

How to control the PIPE mode or serial mode in the example testbench?

Environment

  • PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    One parameter, serial_sim_hwtcl, in the altprice_tbed_sv_hwtcl.v file, controls whether the testbench simulates in PIPE mode or serial mode. When is set to 0, the simulation runs in PIPE mode; when set to 1, it runs in serial mode.

    Resolution

     

    Related Products

    This article applies to 1 products

    Stratix® V GX FPGA