Article ID: 000079613 Content Type: Product Information & Documentation Last Reviewed: 09/12/2012

How to control the PIPE mode or serial mode in the example testbench?

Environment

    PCI Express
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Description

One parameter, serial_sim_hwtcl, in the altprice_tbed_sv_hwtcl.v file, controls whether the testbench simulates in PIPE mode or serial mode. When is set to 0, the simulation runs in PIPE mode; when set to 1, it runs in serial mode.

Resolution

 

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Stratix® V GX FPGA

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