Article ID: 000079611 Content Type: Troubleshooting Last Reviewed: 10/10/2011

IP Compiler for PCI Express Qsys-Generated VHDL Testbench Cannot Simulate

Environment

    Quartus® II Subscription Edition
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Critical Issue

Description

Qsys cannot generate a functional VHDL testbench for an IP Compiler for PCI Express.

This issue affects all IP Compiler for PCI Express variations generated in Qsys with a VHDL testbench.

Resolution

To avoid this issue, generate and simulate your design with the Verilog HDL testbench.

This issue will be fixed in a future version of the IP Compiler for PCI Express.

Related Products

This article applies to 1 products

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