Article ID: 000079587 Content Type: Troubleshooting Last Reviewed: 11/04/2013

ECC Not Enabled in Cyclone V SoC HPS Devices

Environment

    Quartus® II Subscription Edition
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Critical Issue

Description

This problem affects DDR2, DDR3, and LPDDR2 products.

For HPS hard memory controller interfaces in Cyclone V SoC HPS devices, interface widths of 24 (16 plus ECC) and 40 (32 plus ECC) are not supported, because the preloader generator does not enable ECC.

Resolution

The workaround for this issue is to use non-ECC interface widths of 8, 16, or 32.

This issue will be fixed in a future release.

Related Products

This article applies to 1 products

Cyclone® V FPGAs and SoC FPGAs

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