Article ID: 000079556 Content Type: Troubleshooting Last Reviewed: 11/23/2011

Simulation Fails with PLL Clocks Out of Synchronization for UniPHY External Memory Interfaces

Environment

  • Quartus® II Subscription Edition
  • PLL
  • Simulation
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    During simulation, the PLL clocks lose synchronization.

    Resolution

    To work around this issue, follow these steps:

    1. In text editor open the design file and remove the following line: coverage exclude_file
    2. In the ALTPLL MegaWizard interface, turn on Create output files using the Advanced PLL parameters and regenerate the PLL ().

    Related Products

    This article applies to 1 products

    Intel® Programmable Devices

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