Article ID: 000079490 Content Type: Product Information & Documentation Last Reviewed: 03/16/2023

How does the PLL Intel FPGA IP behave when the areset port is toggled and is there a requirement for when areset can be toggled next?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

On the rising edge (assertion) of the phase locked loop (PLL) areset pin, all PLL counters are cleared and the VCO is set to a nominal center frequency.  To ensure the correct operation of the PLL there is a state machine that operates from the input clock to the PLL (refclk) to control the timing of the internal resets.

The state machine begins the process of taking the PLL out of reset from the falling edge of areset.  This process requires 1,024 refclk cycles to complete.  Any rising edges of areset will be ignored during these 1,024 refclk cycles and the PLL will not be held in reset.

Resolution

Do not reassert areset within 1,024 refclk cycles of it being deasserted.

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