Yes. there is an issue with how the RLDRAMII UniPHY based IP interprets the board skew parameters in Quartus® II software 11.0SP1. The board skew parameters are not properly entered in the {core_name}_p0_timing.tcl file.
For example, If you enter 20ps for “Average delay difference between Address/Command and CK, the <core_name>_p0_timing.tcl script properly constrains it with the following constraint
set board(addresscmd_CK_skew) [expr { 20 / 1000.0 }]
But if you enter 20ps for “Maximum skew within Address/Command bus”, the
{core_name}_p0_timing.tcl puts the following incorrect constraint.
set board(intra_addr_ctrl_skew) [expr { 0.02 / 1000.0 }]
This constraint implies that the skew is 0.02ps instead of 20ps for the parameter.
To workaround this issue, make the change manually and change the constraint to:
set board(intra_addr_ctrl_skew) [expr { 20 / 1000.0 }]
This issue will be fixed in the future version of the Quartus II software and the IP.