Why does signal detect fail in an Cadence NCSim simulation when switching between Gen1 and Gen3 using the PHY IP Core for PCI Express?

When simulating the PHY IP Core for PCI Express with Cadence NCSim targeting the Stratix® V device family, the PCIe link may fail to detect a receiver when switching between Gen1 and Gen3 multiple times.  In the failing case, pipe_rxvalid will fail to go high and signal detection will fail. 

This issue is caused by a problem in the encrypted simulation files. 

To solve the issue. follow these steps:

1. Download the following fixed encrypted simulation model:

• stratix_hssi_atoms_ncrypt (.v file)

2. Replace the file with the same name in the following directory:

      <Quartus II software installation directory>\eda\sim_lib\cadence\

This issue will be fixed in a future version of the Quartus® II software.