Article ID: 000079456 Content Type: Error Messages Last Reviewed: 03/07/2023

Error: Could not place fractional PLLaltlvds_serdes_tx_side:<Instance_name>pll_fclk~FRACTIONAL_PLL



You may see this error when using the ALTLVDS_TX or ALTLVDS_RX mega function for Stratix® V device designs in the Quartus® II software versions 10.0, 10.0 SP1, 10.1, and 10.1 SP1. 

This error can occur even when there are enough fPLL resources to place the design.  A problem with the Intel® Quartus® II fitter prevents it from successfully placing the design resources.


You can work around this problem by assigning pin location to the clock input pin, the ALTLVDS_TX transmitters, and the ALTLVDS_RX receivers.  You can make specific pin location assignments or general location assignments such as "EDGE_TOP" or "EDGE_BOTTOM."  Once you make location assignments to the clock input, transmitters, and receivers, the design should be able to fit, provided the required resources are available in the selected device.

This is fixed in version 11.0 of the Intel® Quartus® II software.

Related Products

This article applies to 4 products

Stratix® V E FPGA
Stratix® V GX FPGA
Stratix® V GT FPGA
Stratix® V GS FPGA