Article ID: 000079448 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Is it possible for my external output clock to glitch while the output clock is disabled using the clock enable (e#_ena) port?


  • PLL


    A pulse can be seen on the output clock of the PLL even though the clock enable signal has disabled the clock output. The circuit for the clock enable is as follows:

    Figure 1.  Circuit for Clock Enable

    Figure 1. Circuit for Clock Enable

    If the PLL is reset before the clock is disabled, there is a chance that the output clock will glitch.  When the PLL is in reset, the output clock from the counter is disabled.  From the circuit above, the clkena is registered on the negative edge of the clock coming out of the counters.  If the PLL is placed in to reset the clkena register will hold its value at high.  The clkena is then brought low but the register will still have a value of high.  When the PLL is brought out of reset, the counters will start to count again.  Since the clkena is not registered until the negative edge, a signal pulse on the clock output will be seen.  The waveform below shows this behavior.

    Figure 2. Altera Hot-Socketing Test Setup

    Figure 2. Altera Hot-Socketing Test Setup

    To prevent this glitch from occurring, the clkena signal should always be brought low before the PLL is put into reset.

    Related Products

    This article applies to 1 products

    Stratix® FPGAs