Article ID: 000079429 Content Type: Troubleshooting Last Reviewed: 11/15/2011

Clock mem_cq_n Not Used for QDR Interfaces on Arria V and Cyclone V

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    In QDR II and QDR II SRAM Controllers with UniPHY targeting Arria V or Cyclone V devices, with read latency not equal to 2, the complimentary clock mem_cq_n is not used for capture, therefore the pin is unused.

    In cases where read latency equals 2, mem_cq_n serves as the capture clock and mem_cq is unused.

    This issue affects QDR II and QDR II SRAM Controllers targeting Arria V and Cyclone V devices, where read latency does not equal 2.

    Resolution

    There is no workaround for this issue.

    Related Products

    This article applies to 2 products

    Arria® V FPGAs and SoC FPGAs
    Cyclone® V FPGAs and SoC FPGAs