Avalon-MM Master Interface Captures Data From Avalon-MM Slave in the JESD204B IP Core One Clock Cycle Earlier Than Expected

When you use the Quartus II software Qsys tool to connect the Avalon-MM Master interface to the Avalon-MM Slave interface in the JESD204B IP core, you will not be able to read data at the Avalon-MM Master side during a read operation.

When the waitrequest port is present, the readLatency signal (default value = 0) takes precedence over the readWaitTime signal (default value = 1). For the JESD204B Avalon MM Slave interface, data is captured at the readdata port one clock cycle after receiving the read command. This behavior causes the Qsys interconnect to capture data from the JESD204B Avalon-MM Slave one clock cycle earlier than expected.

This issue affects all versions that support the JESD204B IP core.

Set the readLatency signal to 1 for all JESD204B Avalon-MM Slave interfaces by following the steps below:

1. Open the altera_jesd204_tx_hw.tcl file located in the <quartus_directory>/acds/ip/altera/altera_jesd204/src/tx directory and add the following code at line 89:

“set_interface_property jesd204_tx_avs readLatency 1”

2. Open the altera_jesd204_rx_hw.tcl file located in the <quartus_directory>/acds/ip/altera/altera_jesd204/src/rx directory and add the following code at line 87:

“set_interface_property jesd204_rx_avs readLatency 1”