Article ID: 000079368 Content Type: Troubleshooting Last Reviewed: 04/15/2013

Why does the TimeQuest timing analyzer not report setup and hold timing for the signal phasestep for Stratix III and Stratix IV designs using PLL reconfiguration?


  • Quartus® II Subscription Edition
  • PLL

    For Stratix® III and Stratix IV designs using PLL reconfiguration, the TimeQuest timing analyzer does not report setup or hold values for the signal phasestep because the timing for this signal is not critical.

    The Stratix III Device Handbook chapter Clock Networks and PLLs in Stratix III Devices (PDF) and the Stratix IV Device Handbook chapter Clock Networks and PLLs in Stratix IV Devices (PDF) indicate that all PLL reconfiguration signals are synchronous to scanclk, and that all signals should meet setup and hold in relation to scanclk. However, the signal phasestep should be held for multiple cycles of scanclk and deasserted only after the signal phasedone goes low. The correct usage of phasestep is also documented in Application Note 454: Implementing PLL Reconfiguration in Stratix III and Stratix IV Devices (PDF). Because the signal is used in this manner, setup and hold analysis is not required for phasestep.


    The device handbooks are scheduled to be updated to clarify the timing requirements for PLL reconfiguration signals.

    Related Products

    This article applies to 4 products

    Stratix® IV E FPGA
    Stratix® IV GT FPGA
    Stratix® IV GX FPGA
    Stratix® III FPGAs



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