Critical Issue
You may see this error in DSP Builder v13.1 and later, if you compile your design that DSP Builder v13.0 and earlier generated in the Quartus II software version 13.1 and later. A new parameter in the Pipelined Adder block v13.1 causes the error. This problem affects the Altera DSP Builder Standard Blockset only .
To work around this problem:
- In your directory where DSP Builder generated HDL is located, open alt_dspbuilder_sLpmAddSub.vhd
- Add the following line to the list of generics in alt_dspbuilder_sLpmAddSub entity declaration
\'or_aclr_inputs : boolean := true\'
Note: This workaround does not affect the behavior of your HDL.
This problem is scheduled to be fixed in a future version of DSP Builder