Article ID: 000079334 Content Type: Troubleshooting Last Reviewed: 04/24/2023

Is there a known problem with Intel® Arria® 10 fPLL simulation when the clock switchover feature is enabled?

Environment

    Quartus® II Subscription Edition
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Description

Due to a known problem in the Quartus® II software version 14.1 and earlier, you may see an incorrect output clock when simulating an Arria® 10 fPLL with the clock switchover feature enabled.

 

 

Resolution

This issue is scheduled to be fixed in a future release of the Quartus® II software.

Related Products

This article applies to 3 products

Intel® Arria® 10 GX FPGA
Intel® Arria® 10 GT FPGA
Intel® Arria® 10 SX SoC FPGA

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