Description
FIR Compiler II currently generates source files that include both VHDL and Verilog. Selecting Verilog HDL in the MegaWizard™ only changes the top level wrapper of the FIR Compiler II variation.
Simulation failure using a single-lanaguage simulator is also covered in the MegaCore IP Release Notes and Errata.
This issue will be fixed in a future version of the software.