Article ID: 000079288 Content Type: Troubleshooting Last Reviewed: 11/15/2013

What is the size of the instruction cache on the HPS DMA Contoller in Cyclone V and Arria V SOC devices?

Environment

  • Quartus® II Subscription Edition
  • DMA
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The instruction cache size of the ARM DMA-330  IP on Cyclone® and Arria® V series SOC devices is 512 bytes.

    The cache line size is 8 words (4 bytes each), resulting in a line size of 32 bytes. 

    There are a total of 16 cache lines, giving a total of 512 bytes.

     

    Resolution This information is scheduled to be included in a future update to the Cyclone V and Arria V HPS Technical Reference Manuals.

    Related Products

    This article applies to 5 products

    Cyclone® V SE SoC FPGA
    Arria® V ST SoC FPGA
    Arria® V SX SoC FPGA
    Cyclone® V ST SoC FPGA
    Cyclone® V SX SoC FPGA

    Need more help?

    Contact support

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.