Article ID: 000079283 Content Type: Product Information & Documentation Last Reviewed: 01/01/2015

How can I make the HPS SPI Master SS signal stay low for the whole transaction period?

Environment

    Quartus® II Subscription Edition
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Description

Some SPI Slaves may require the SPI Master to hold the SS line low during the whole SPI transaction period. The HPS SPI Master can be configured to function in that manner with workaround below.

Resolution

With reference to HPS address map in http://www.altera.com/literature/hb/cyclone-v/hps.html,  set spim0->ctrlr0->scph [bit 6] to 1.

Related Products

This article applies to 5 products

Arria® V ST SoC FPGA
Arria® V SX SoC FPGA
Cyclone® V SX SoC FPGA
Cyclone® V SE SoC FPGA
Cyclone® V ST SoC FPGA

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