Article ID: 000079268 Content Type: Troubleshooting Last Reviewed: 04/02/2014

Why can't I observe any activity on the Triple Speed Ethernet MegaCore Function’s RGMII_OUT signals in the SignalTap II Logic Analyzer?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The RGMII_OUT registers are implemented using Alt DDIO_OUT atoms which cannot be observed using SignalTap™ as a routing path to the core is not possible. Hence it is not possible to signaltap these nodes.

In the SignalTap II Logic Analyzer, the RGMII_OUT signals are only visible by selecting “SignalTap II: pre-synthesis” as filter, however after compilation, from the Compilation Report > Analysis & Synthesis > In-System Debugging, you will find that the status of the RGMII_OUT signals are illegal and these signals are connected to GND.

If you change SignalTap II’s filter to “SignalTap II: post-fit”, you are unable to find the RGMII_OUT signals.

Resolution

The functionality of the RGMII_OUT  (DDIO_OUT) block is unaffected and you are able to scope the output signal on your board.

Related Products

This article applies to 32 products

Intel® Arria® 10 GT FPGA
Intel® Arria® 10 GX FPGA
Intel® Arria® 10 SX SoC FPGA
Arria® GX FPGA
Arria® II GX FPGA
Arria® II GZ FPGA
Arria® V GT FPGA
Arria® V GX FPGA
Arria® V GZ FPGA
Arria® V ST SoC FPGA
Cyclone® II FPGA
Cyclone® III FPGAs
Cyclone® III LS FPGA
Cyclone® IV E FPGA
Cyclone® IV GX FPGA
Cyclone® V E FPGA
Cyclone® V GT FPGA
Cyclone® V GX FPGA
Cyclone® V SE SoC FPGA
Cyclone® V ST SoC FPGA
Cyclone® V SX SoC FPGA
Intel® Stratix® 10 GX FPGA
Intel® Stratix® 10 SX SoC FPGA
Stratix® II FPGAs
Stratix® II GX FPGA
Stratix® III FPGAs
Stratix® IV E FPGA
Stratix® IV GT FPGA
Stratix® V E FPGA
Stratix® V GS FPGA
Stratix® V GT FPGA
Stratix® V GX FPGA

1

Need more help?

Contact support

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.