Article ID: 000079255 Content Type: Troubleshooting Last Reviewed: 05/25/2023

* Error: Module parameter 'CFG_CMD_GEN_OUTPUT_REG' not found for override at alt_mem_ddrx_controller.v

Environment

    Quartus® II Subscription Edition
    DDR3 SDRAM Controller with UniPHY Intel® FPGA IP
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You might see the above error when simulating your DDR3 UniPHY controller with the ModelSim-Intel® FPGA. The cause of the error is the ordering of the compilation libraries in the ModelSim vsim elaboration call.

Resolution

You must make sure the library containing the DDR3 compiled files is listed first in the command. In this case, the work directory contains the DDR3 compiled files:

vsim -novopt -t ps -L work -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L altera_mf -L altera_lnsim -L stratixiv <top_level_filename>

It is recommended that you follow the file and library ordering in the msim_setup.tcl file provided in the <IP_variation_name>_sim/mentor directory.

Related Products

This article applies to 20 products

Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA
Stratix® V GX FPGA
Stratix® V GT FPGA
Cyclone® V GX FPGA
Stratix® V GS FPGA
Arria® V GZ FPGA
Arria® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Arria® V ST SoC FPGA
Arria® V GX FPGA
Arria® V GT FPGA
Arria® II GZ FPGA
Stratix® III FPGAs
Stratix® IV GX FPGA
Stratix® IV GT FPGA
Cyclone® V E FPGA
Stratix® V E FPGA
Stratix® IV E FPGA
Cyclone® V SE SoC FPGA

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