Article ID: 000079235 Content Type: Troubleshooting Last Reviewed: 12/07/2015

Why does DSP builder advance synthesisInfo block fail to constrain the latency when it is specified?

Environment

    Quartus® II Subscription Edition
    DSP Builder for Intel® FPGAs Pro Edition
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

When using the synthesisInfo block in the DSP Builder Advanced library, the latency can only be constrained between the ChannelIn and ChannelOut block.

 

Resolution

If you are using GPIN and GPOUT bock as an interface to your subsystem, the synthesisInfo block latency constraint will not be taken into account, unless they are replaced by a pair of ChannelIn and ChannelOut block.

 

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This article applies to 1 products

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